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74 lines
2.8 KiB
74 lines
2.8 KiB
package arm64 |
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import ( |
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"github.com/segmentio/asm/cpu/cpuid" |
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. "golang.org/x/sys/cpu" |
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) |
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type CPU cpuid.CPU |
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func (cpu CPU) Has(feature Feature) bool { |
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return cpuid.CPU(cpu).Has(cpuid.Feature(feature)) |
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} |
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func (cpu *CPU) set(feature Feature, enable bool) { |
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(*cpuid.CPU)(cpu).Set(cpuid.Feature(feature), enable) |
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} |
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type Feature cpuid.Feature |
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const ( |
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FP Feature = 1 << iota // Floating-point instruction set (always available) |
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ASIMD // Advanced SIMD (always available) |
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EVTSTRM // Event stream support |
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AES // AES hardware implementation |
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PMULL // Polynomial multiplication instruction set |
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SHA1 // SHA1 hardware implementation |
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SHA2 // SHA2 hardware implementation |
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CRC32 // CRC32 hardware implementation |
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ATOMICS // Atomic memory operation instruction set |
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FPHP // Half precision floating-point instruction set |
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ASIMDHP // Advanced SIMD half precision instruction set |
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CPUID // CPUID identification scheme registers |
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ASIMDRDM // Rounding double multiply add/subtract instruction set |
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JSCVT // Javascript conversion from floating-point to integer |
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FCMA // Floating-point multiplication and addition of complex numbers |
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LRCPC // Release Consistent processor consistent support |
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DCPOP // Persistent memory support |
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SHA3 // SHA3 hardware implementation |
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SM3 // SM3 hardware implementation |
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SM4 // SM4 hardware implementation |
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ASIMDDP // Advanced SIMD double precision instruction set |
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SHA512 // SHA512 hardware implementation |
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SVE // Scalable Vector Extensions |
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ASIMDFHM // Advanced SIMD multiplication FP16 to FP32 |
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) |
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func ABI() CPU { |
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cpu := CPU(0) |
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cpu.set(FP, ARM64.HasFP) |
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cpu.set(ASIMD, ARM64.HasASIMD) |
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cpu.set(EVTSTRM, ARM64.HasEVTSTRM) |
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cpu.set(AES, ARM64.HasAES) |
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cpu.set(PMULL, ARM64.HasPMULL) |
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cpu.set(SHA1, ARM64.HasSHA1) |
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cpu.set(SHA2, ARM64.HasSHA2) |
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cpu.set(CRC32, ARM64.HasCRC32) |
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cpu.set(ATOMICS, ARM64.HasATOMICS) |
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cpu.set(FPHP, ARM64.HasFPHP) |
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cpu.set(ASIMDHP, ARM64.HasASIMDHP) |
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cpu.set(CPUID, ARM64.HasCPUID) |
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cpu.set(ASIMDRDM, ARM64.HasASIMDRDM) |
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cpu.set(JSCVT, ARM64.HasJSCVT) |
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cpu.set(FCMA, ARM64.HasFCMA) |
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cpu.set(LRCPC, ARM64.HasLRCPC) |
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cpu.set(DCPOP, ARM64.HasDCPOP) |
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cpu.set(SHA3, ARM64.HasSHA3) |
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cpu.set(SM3, ARM64.HasSM3) |
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cpu.set(SM4, ARM64.HasSM4) |
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cpu.set(ASIMDDP, ARM64.HasASIMDDP) |
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cpu.set(SHA512, ARM64.HasSHA512) |
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cpu.set(SVE, ARM64.HasSVE) |
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cpu.set(ASIMDFHM, ARM64.HasASIMDFHM) |
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return cpu |
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}
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