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76 lines
3.3 KiB
76 lines
3.3 KiB
package x86 |
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import ( |
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"github.com/segmentio/asm/cpu/cpuid" |
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. "golang.org/x/sys/cpu" |
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) |
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type CPU cpuid.CPU |
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func (cpu CPU) Has(feature Feature) bool { |
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return cpuid.CPU(cpu).Has(cpuid.Feature(feature)) |
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} |
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func (cpu *CPU) set(feature Feature, enable bool) { |
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(*cpuid.CPU)(cpu).Set(cpuid.Feature(feature), enable) |
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} |
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type Feature cpuid.Feature |
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const ( |
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SSE Feature = 1 << iota // SSE functions |
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SSE2 // P4 SSE functions |
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SSE3 // Prescott SSE3 functions |
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SSE41 // Penryn SSE4.1 functions |
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SSE42 // Nehalem SSE4.2 functions |
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SSE4A // AMD Barcelona microarchitecture SSE4a instructions |
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SSSE3 // Conroe SSSE3 functions |
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AVX // AVX functions |
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AVX2 // AVX2 functions |
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AVX512BF16 // AVX-512 BFLOAT16 Instructions |
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AVX512BITALG // AVX-512 Bit Algorithms |
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AVX512BW // AVX-512 Byte and Word Instructions |
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AVX512CD // AVX-512 Conflict Detection Instructions |
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions |
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions |
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AVX512F // AVX-512 Foundation |
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions |
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AVX512PF // AVX-512 Prefetch Instructions |
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions |
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2 |
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AVX512VL // AVX-512 Vector Length Extensions |
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AVX512VNNI // AVX-512 Vector Neural Network Instructions |
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q |
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword |
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CMOV // Conditional move |
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) |
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func ABI() CPU { |
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cpu := CPU(0) |
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cpu.set(SSE, true) // TODO: golang.org/x/sys/cpu assumes all CPUs have SEE? |
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cpu.set(SSE2, X86.HasSSE2) |
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cpu.set(SSE3, X86.HasSSE3) |
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cpu.set(SSE41, X86.HasSSE41) |
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cpu.set(SSE42, X86.HasSSE42) |
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cpu.set(SSE4A, false) // TODO: add upstream support in golang.org/x/sys/cpu? |
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cpu.set(SSSE3, X86.HasSSSE3) |
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cpu.set(AVX, X86.HasAVX) |
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cpu.set(AVX2, X86.HasAVX2) |
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cpu.set(AVX512BF16, X86.HasAVX512BF16) |
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cpu.set(AVX512BITALG, X86.HasAVX512BITALG) |
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cpu.set(AVX512BW, X86.HasAVX512BW) |
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cpu.set(AVX512CD, X86.HasAVX512CD) |
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cpu.set(AVX512DQ, X86.HasAVX512DQ) |
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cpu.set(AVX512ER, X86.HasAVX512ER) |
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cpu.set(AVX512F, X86.HasAVX512F) |
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cpu.set(AVX512IFMA, X86.HasAVX512IFMA) |
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cpu.set(AVX512PF, X86.HasAVX512PF) |
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cpu.set(AVX512VBMI, X86.HasAVX512VBMI) |
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cpu.set(AVX512VBMI2, X86.HasAVX512VBMI2) |
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cpu.set(AVX512VL, X86.HasAVX512VL) |
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cpu.set(AVX512VNNI, X86.HasAVX512VNNI) |
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cpu.set(AVX512VP2INTERSECT, false) // TODO: add upstream support in golang.org/x/sys/cpu? |
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cpu.set(AVX512VPOPCNTDQ, X86.HasAVX512VPOPCNTDQ) |
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cpu.set(CMOV, true) // TODO: golang.org/x/sys/cpu assumes all CPUs have CMOV? |
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return cpu |
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}
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